1. Field of the Invention
The present invention relates to a delay circuit that delays an input signal to output the signal and a test apparatus that tests a device under test. More particularly, the present invention relates to a delay circuit in which a plurality of delay elements is serially connected to one another.
2. Description of Related Art
Conventionally, a circuit that dulls a waveform of an input signal to delay the input signal by a predetermined delay amount has been known as a delay circuit for delaying the input signal. For example, there has been known a delay circuit that inputs an input signal into an inverter, charges and discharges load capacitance of the inverter, and outputs a voltage waveform in the load capacitance. The delay circuit adjusts rising time and falling time of the voltage waveform in the load capacitance and controls a delay amount to be given to the input signal by controlling a power source current of the inverter to control a charging and discharging current of the load capacitance.
However, when a conventional delay circuit has a large delay amount, a pulse from the delay circuit may become unsteady. For example, when the delay circuit charging and discharging the load capacitance has a large delay amount, a current value charging the load capacitance is reduced. The delay circuit charges the load capacitance for a period for which a pulse of the input signal shows an H-logic. However, since the charging current is small, the voltage of the load capacitance may not stand at a predetermined reference value or the time for which the voltage of the load capacitance stands at a value more than the reference value may not acquire sufficiently.
For such a problem, it is considered that a plurality of delay circuits is serially connected to one another and each delay circuit has a delay amount within a range in which a pulse is stable. However, in such a configuration, a waveform output from each delay circuit gets dull. Each delay circuit turns on/off its CMOS transistor according to the voltage of the input signal and charges and discharges the load capacitance by a power source current according to a delay setting. However, when the waveform of the signal received from the delay circuit in a previous stage gets dull, the timing in which the voltage enough to flow the power source current according to the delay setting is applied to the CMOS transistor gets late. Thus, the delay time in the delay circuit has an error with respect to the delay setting. Therefore, linearity for delay in the delay circuit has deteriorated.